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? freescale semiconductor, inc., 20 05, 2006, 2007. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc13202 rev. 1.2, 05/2007 mc13202 package information plastic package case 1311-03 ordering information device device marking package mc13202 13202 qfn-32 1 introduction the mc13202 is a short range, low power, 2.4 ghz industrial, scientific, and medical (ism) band transceivers. the mc13202 contains a complete 802.15.4 physical layer (phy) modem designed for the ieee ? 802.15.4 standard which supports peer-to-peer, star, and mesh networking. the mc13202 includes the 802.15.4 phy/mac for use with the hcs08 family of mcus. the mc13202 can be used with freescale?s ieee 802.15.4 mac and beestack, which is freesca le?s zigbee 2006 compliant protocol stack. when combined with an a ppropriate microcontroller (mcu), the mc13202 provides a cost-effective solution for short-range data links and networks. interface with the mcu is accomplished using a four wire serial peripheral interface (spi) c onnection and an interrupt request output which allows for the use of a variety of processors. the software and processor can be scaled to fit applications ranging fr om simple point-to-point systems, through complete zigbee? networking. for more detailed information about mc13202 operation, mc13202 2.4 ghz low power transceiver for the ieee ? 802.15.4 standard contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 4 data transfer modes . . . . . . . . . . . . . . . . . . . 5 5 electrical characteristics . . . . . . . . . . . . . . . 8 6 functional description . . . . . . . . . . . . . . . . 12 7 pin connections . . . . . . . . . . . . . . . . . . . . . . 15 8 crystal oscillator reference frequency . . 19 9 transceiver rf configurations and external connections 22 10packaging information . . . . . . . . . . . . . . . . 29
mc13202 technical data, rev. 1.2 2 freescale semiconductor refer to the mc13202 reference manual , (mc13202rm). applications include, but are not limited to, the following: ? residential and commercial automation ? lighting control ? security ? access control ? heating, ventilation, air-conditioning (hvac) ? automated meter reading (amr) ? industrial control ? asset tracking and monitoring ? homeland security ? process management ? environmental mon itoring and control ? hvac ? automated meter reading ? health care ? patient monitoring ? fitness monitoring ? consumer ? human interface devices (keyboard, mice, etc.) ? remote control ? wireless toys the transceiver includes a low noise amplifier, 1.0 mw power amplifiers (pa), onboard rf transmit/receive (t/r) switch for single port use, pll with internal voltage cont rolled oscillator (vco), on-board power supply regulation, and full spread-s pectrum encoding and dec oding. the device supports 250 kbps offset-quadrature phase shift keying (o-qpsk) data in 2.0 mhz channels with 5.0 mhz channel spacing per the 802.15.4 standard. the spi port a nd interrupt request output are used for receive (rx) and transmit (tx) da ta transfer and control. 2features ? recommended power supply range: 2.0 to 3.4 v ? fully compliant 802.15.4 standard transceiver supports 250 kbps o-qpsk data in 5.0 mhz channels and full spread-spectrum encode and decode ? operates on one of 16 selectable channels in the 2.4 ghz band ? -1 to 0 dbm nominal output power, program mable from -27 dbm to +3 dbm typical ? receive sensitivity of <-92 dbm (typical) at 1% per, 20-byte packet, much better than the 802.15.4 standard of -85 dbm
mc13202 technical data, rev. 1.2 freescale semiconductor 3 ? integrated transm it/receive switch ? dual pa output pairs which can be programmed for full differen tial single port or dual port operation that supports an external lna and/or pa ? three power down modes for increased battery life ? < 1 a off current ? 1.0 a typical hibernate current ? 35 a typical doze current (no clko) ? programmable frequency clock output (clko) for use by mcu ? onboard trim capability for 16 mhz crystal refere nce oscillator eliminates need for external variable capacitors and allows for automated production fre quency calibration ? four internal timer comparators availa ble to supplement mcu timer resources ? supports both packet mode and streaming mode data transfer ? buffered transmit and receive data packet s for simplified use with low cost mcus ? seven gpio to supplement mcu gpio ? operating temperature range: -40 c to 85 c ? small form factor qfn-32 package ? meets moisture sensitivity level (msl) 3 ? 260 c peak reflow temperature ? meets lead-free requirements 2.1 software features freescale provides a wide range of software functionality to comp lement the mc13202 hardware. there are three levels of application solutions: 1. simple proprietary wireless connectivity. 2. user networks built on the 802.15.4 mac standard. 3. zigbee-compliant network stack. 2.1.1 simple mac (smac) ? small memory footprint (about 3 kbytes typical) ? supports point-to-point and st ar network configurations ? proprietary networks ? source code and applicat ion examples provided
mc13202 technical data, rev. 1.2 4 freescale semiconductor 2.1.2 802.15.4 standard-compliant mac ? supports star, mesh and cluster tree topologies ? supports beaconed networks ? supports gts for low latency ? multiple power saving mode s (idle doze, hibernate) 2.1.3 zigbee-compliant network stack ? supports zigbee 1.0 specification ? supports star, mesh and tree networks ? advanced encryption standa rd (aes) 128-bit security 3 block diagrams figure 1 shows a simplified block diagram of the mc13202 which is an 802.15.4 standard compatible transceiver that provides the functions requir ed in the physical layer (phy) specification. figure 1. 802.15.4 modem simplified block diagram phase shift modulator rst gpio1 gpio2 gpio3 gpio4 xtal2 xtal1 rfin_m (pao_m) pao_p pao_m mosi miso spiclk rxtxen ce attn gpio5 gpio6 gpio7 receive packet ram transmit packet ram 1 transmit ram arbiter receive ram arbiter pa vco crystal oscillator sy mbol generation fcs generation header generation mux sequence manager (control logic) vd d lo2 4 256 mhz 2.45 ghz lna 1st if mix er if = 65 mhz 2nd if mix er if = 1 mhz pma decimation filter matched filter baseband mixer dcd correlator symbol synch & det cca packet processor irq arbiter 24 bit ev ent timer irq 16 mhz agc analog regulator vbatt digital regulator l digital regulator h pow er-up control logic crystal regulator vco regulator vddint programmable prescaler clko 4 programmable timer comparators sy nthesizer vddd vddvco serial peripheral interface (spi) vdda vddlo1 transmit packet ram 2 t / r rfin_p (pao_p) ct_bias
mc13202 technical data, rev. 1.2 freescale semiconductor 5 figure 2 shows the basic system block diagram for th e mc13202 in an application. interface with the transceiver is accomplished through a 4-wire spi port and inte rrupt request line. the media access control (mac), drivers, and network and a pplication software (as required) re side on the host processor. the host can vary from a simple 8-bit devi ce up to a sophisticated 32-bit processor depending on application requirements. figure 2. system level block diagram 4 data transfer modes the mc13202 has two da ta transfer modes: 1. packet mode ? data is buffered in on-chip ram 2. streaming mode ? data is processed word-by-word the freescale 802.15.4 mac softwa re only supports the streaming mode of data transfer. for proprietary applications, packet mode can be used to conserve mcu resources. 4.1 packet structure figure 3 shows the packet structure of the mc13202. pa yloads of up to 125 bytes are supported. the mc13202 adds a four-byte preamble, a one-byte start of fr ame delimiter (sfd), and a one-byte frame length indicator (fli) befo re the data. a frame check sequence (fcs) is calcul ated and appended to the end of the data. figure 3. mc13202 packet structure analog receiver mc13202 frequency generation analog transmitter voltage regulators power up management control logic buffer ram digital transceiver spi and gpio microcontroller spi rom (flash) ram cpu a/d timer application irq arbiter ram arbiter timer network mac phy driver preamble sfd fli payload data fcs 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
mc13202 technical data, rev. 1.2 6 freescale semiconductor 4.2 receive path description in the receive signal path, the rf input is converted to low if in-phase and qu adrature (i & q) signals through two down-conversion stages. a clear channel assessment (cca ) can be performed based upon the baseband energy integrated over a specific time in terval. the digital backe nd performs differential chip detection (dcd), the correlat or ?de-spreads? the di rect sequence spread sp ectrum (dsss) offset qpsk (o-qpsk) signal, determines the sy mbols and packets, and detects the data. the preamble, sfd, and fli are parsed and used to de tect the payload data and fcs which are stored in ram. a two-byte fcs is calculated on the received data and compared to the fcs value appended to the transmitted data, which generates a cyclical redundancy check (crc) result. link quality is measured over a 64 s period after the packet preamble and stored in ram. if the mc13202 is in packet mode, the data is processed as an entire packet. the mc u is notified that an entire packet has been r eceived via an interrupt. if the mc13202 is in streaming mode, the mcu is notified by an interrupt on a word-by-word basis. figure 4 shows cca reported power level versus input power. note th at cca reported power saturates at about -57 dbm input power which is we ll above 802.15.4 standa rd requirements. figure 5 shows energy detection/lqi reported le vel versus input power. note for both graphs, the required 802.15.4 standard accuracy and range limits are shown. a 3.5 dbm offset has been programmed into the cca reporting level to center the level ove r temperature in the graphs. figure 4. reported power level versus input power in cca mode -100 -90 -80 -70 -60 -50 -90 -80 -70 -60 -50 input pow er (dbm) reported power level (dbm) 802.15.4 accuracy and range requirements
mc13202 technical data, rev. 1.2 freescale semiconductor 7 figure 5. reported power level versus input power for energy detect or link quality indicator 4.3 transmit path description for the transmit path, the tx data th at was previously stored in ram is retrieved (packet mode) or the tx data is clocked in via the spi (s tream mode), formed into packets per the 802.15.4 phy, spread, and then up-converted to the transmit frequency. if the mc13202 is in packet mode, data is processed as an entire packet. the data are first loaded into the tx buffer. the mcu then requests that the mc13202 transmit the data. the mcu is notified via an interrupt when the whole packet ha s successfully been transmitted. in streaming mode, the data is fe d to the mc13202 on a word-by-word basi s with an interrupt serving as a notification that the mc13202 is ready for more da ta. this continues until the whole packet is transmitted. -85 -75 -65 -55 -45 -35 -25 -15 -85 -75 -65 -55 -45 -35 -25 -15 input power level (dbm) reported power level (dbm) 802.15.4 accuracy and range requirements
mc13202 technical data, rev. 1.2 8 freescale semiconductor 5 electrical characteristics 5.1 maximum ratings 5.2 recommended oper ating conditions table 1. maximum ratings rating symbol value unit power supply voltage v batt, v ddint -0.3 to 3.6 vdc digital input voltage vin -0.3 to (v ddint + 0.3) rf input power p max 10 dbm junction temperature t j 125 c storage temperature range t stg -55 to 125 c note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to t he limits in the electrical characteristics or recommended operating conditions tables. note: meets human body model (hbm) = 2 kv. rf in put/output pins have no esd protection. table 2. recommended operating conditions characteristic symbol min typ max unit power supply voltage (v batt = v ddint ) 1 1 if the supply voltage is produced by a switching dc-dc conv erter, ripple should be less than 100 mv peak-to-peak. v batt, v ddint 2.0 2.7 3.4 vdc input frequency f in 2.405 - 2.480 ghz ambient temperature range t a -40 25 85 c logic input voltage low v il 0-30% v ddint v logic input voltage high v ih 70% v ddint -v ddint v spi clock rate f spi --8.0mhz rf input power p max --10dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 16 mhz only
mc13202 technical data, rev. 1.2 freescale semiconductor 9 5.3 dc electrical characteristics table 3. dc electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply current (v batt + v ddint ) off 1 hibernate 1 doze (no clko) 1 2 idle transmit mode (0 dbm nominal output power) receive mode 1 to attain specified low power current, all gpio and other digital io must be handled properly. see section 8.3, ?low power considerations? . 2 clko frequency at default value of 32.786 khz. i leakage i cch i ccd i cci i cct i ccr - - - - - - 0.2 1.0 35 500 30 37 1.0 6.0 102 800 35 42 a a a a ma ma input current (v in = 0 v or v ddint ) (all digital inputs) i in --1 a input low voltage (all digital inputs) v il 0-30% v ddint v input high voltage (all digital inputs) v ih 70% v ddint -v ddint v output high voltage (i oh = -1 ma) (all digital outputs) v oh 80% v ddint -v ddint v output low voltage (i ol = 1 ma) (all digital outputs) v ol 0-20% v ddint v
mc13202 technical data, rev. 1.2 10 freescale semiconductor 5.4 ac electrical characteristics table 4. receiver ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit sensitivity for 1% packet error rate (per) (-40 to +85 c) sens per --92-dbm sensitivity for 1% packet error rate (per) (+25 c) - -92 -87 dbm saturation (maximu m input level) sens max -10-dbm channel rejection for 1% per (desired signal -82 dbm) +5 mhz (adjacent channel) -5 mhz (adjacent channel) +10 mhz (alternate channel) -10 mhz (alternate channel) >= 15 mhz - - - - - 31 30 43 41 53 - - - - - db db db db db frequency error tolerance - - 200 khz symbol rate error tolerance - - 80 ppm table 5. transmitter ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit power spectral density (-40 to +85 c) absolute limit - -47 - dbm power spectral density (-40 to +85 c) relative limit - 47 - nominal output power 1 1 spi register 12 programmed to 0x00bc which sets output power to nominal (-1 dbm typical). p out -4 -1 2 dbm maximum output power 2 2 spi register 12 programmed to 0x00ff which sets output power to maximum. 4dbm error vector magnitude evm - 20 35 % output power control range - 30 - db over the air data rate - 250 - kbps 2nd harmonic - tbd - dbc 3rd harmonic - tbd - dbc
mc13202 technical data, rev. 1.2 freescale semiconductor 11 figure 6 shows a typical ac para meter evaluation circuit. figure 6. rf parametric evaluation circuit table 6. digital timing specifications (vbatt, vddint = 2.7 v, ta = 25 c, frequency = 16 mhz, unless otherwise noted. spi timing parameters are referenced to figure 8 . symbol parameter min typ max unit t0 spiclk period 125 ns t1 pulse width, spiclk low 50 ns t2 pulse width, spiclk high 50 ns t3 delay time, miso data valid from falling spiclk 15 ns t4 setup time, ce low to rising spiclk 15 ns t5 delay time, miso valid from ce low 15 ns t6 setup time, mosi valid to rising spiclk 15 ns t7 hold time, mosi valid from rising spiclk 15 ns rst minimum pulse width low (asserted) 250 ns l2 6.8nh 5 1 6 2 3 4 z1 ldb212g4005c-001 l3 3. 9 n h c1 1.0pf r1 0r r2 0r not mount ed 1 2 5 3 4 j1 s ma_ e d ge _ r ec e p t a c c2 10 p f an t1 f_antenna pao_m 6 pao_p 5 rfin_p 2 rfin_m 1 ct_bias 3 u5 mc 1 32 0 x l1 1.8nh l4 1.8nh
mc13202 technical data, rev. 1.2 12 freescale semiconductor 6 functional description the following sections provide a detailed description of the mc 13202 functionality including the operating modes and serial peripheral interface (spi). 6.1 mc13202 operational modes the mc13202 has a number of operati onal modes that allow for low-cu rrent operation. transition from the off to idle mode occurs when rst is negated. once in idle, the spi is active and is used to control the ic. transition to hibernate and doze modes is en abled via the spi. these modes are summarized, along with the transition times, in table 7 . current drain in the vari ous modes is listed in table 3 , dc electrical characteristics. 6.2 serial peripheral interface (spi) the host microcontroller directs th e mc13202, checks its status, and re ads/writes data to the device through the 4-wire spi port. the transceiver operate s as a spi slave device only. a transaction between the host and the mc13202 occurs as multiple 8-bit bursts on the spi. the spi signals are: 1. chip enable (ce ) - a transaction on the spi port is framed by the active low ce input signal. a transaction is a minimum of 3 spi bursts a nd can extend to a greater number of bursts. 2. spi clock (spiclk) - the host drives the spicl k input to the mc13202. data is clocked into the master or slave on the leading (rising) edge of the return-to-zero spiclk and data out changes state on the trailing (falling) edge of spiclk. note for freescale microcontrollers, the spi clock format is the clock phase control bit cpha = 0 and the clock polarity control bit cpol = 0. 3. master out/slave in (mosi) - incoming data from the host is presented on the mosi input. 4. master in/slave out (miso) - the mc13202 pres ents data to the master on the miso output. table 7. mc13202 mode definitions and transition times mode definition transition time to or from idle off all ic functions off, leakage only. rst asserted. digital outputs are tri-stated including irq 10 - 25 ms to idle hibernate crystal reference oscillator off. (spi not functional.) ic responds to attn . data is retained. 7 - 20 ms to idle doze crystal reference oscillator on but clko out put available only if register 7, bit 9 = 1 for frequencies of 1 mhz or less. (spi not functional.) responds to attn and can be programmed to enter idle mode through an internal timer comparator. (300 + 1/clko) s to idle idle crystal reference oscillator on with clko output available. spi active. receive crystal reference oscillator on. receiver on. 144 s from idle transmit crystal reference oscillator on. transmitter on. 144 s from idle
mc13202 technical data, rev. 1.2 freescale semiconductor 13 a typical interconnection to a microcontroller is shown in figure 7 . figure 7. spi interface although the spi port is fully static, in ternal memory, timer and interrupt arbiters require an internal clock (clk core ), derived from the crystal refere nce oscillator, to communicate from the spi registers to internal registers and memory. 6.2.1 spi burst operation the spi port of an mcu transfers data in bursts of 8 bi ts with most significant bit (msb) first. the master (mcu) can send a byte to the slave (transceiver) on the mosi line and the slave can send a byte to the master on the miso line . although an mc13202 transact ion is three or more spi bursts long, the timing of a single spi burst is shown in figure 8 . figure 8. spi single burst timing diagram spi digital timing specifications are shown in table 6 . shift register baud rate generator shift register chip enable (ce) rxd miso txd mosi sclk spiclk mcu mc13202 ce 1 23 45 678 ce spiclk t1 t2 t4 t0 spi burst valid t5 t6 t3 valid t7 miso mosi valid
mc13202 technical data, rev. 1.2 14 freescale semiconductor 6.2.2 spi transaction operation although the spi port of an mcu transfers data in bur sts of 8 bits, the mc13202 requires that a complete spi transaction be framed by ce , and there will be three (3) or more bursts per transaction. the assertion of ce to low signals the start of a tr ansaction. the first spi burst is a write of an 8-bit header to the transceiver (mosi is valid) that defines a 6-bit address of the in ternal resource being accessed and identifies the access as being a read or write operation. in this context, a write is data written to the mc13202 and a read is data written to the spi master . the following spi bursts will be either the write data (mosi is valid) to the transceiver or r ead data from the transceiver (miso is valid). although the spi bus is capable of sending data simultaneously betw een master and slave, the mc13202 never uses this mode. the number of data bytes (paylo ad) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. the number of payload bytes sent will always be an even integer. after the final spi burst, ce is negated to high to signal the e nd of the transaction. refer to the mc13202 reference manual , (mc13202rm) for more details on sp i registers and transaction types. an example spi read transaction wi th a 2-byte payload is shown in figure 9 . figure 9. spi read transaction diagram ce spiclk miso mosi valid valid v alid clock burst header read data
mc13202 technical data, rev. 1.2 freescale semiconductor 15 7 pin connections table 8. pin function description pin # pin name type description functionality 1 rfin_m rf input rf input/output negative. when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa 2 rfin_p rf input rf input/output positive. when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa 3 ct_bias control voltage bias voltage/control signal for external rf components when used with internal t/r switch, provides rx ground reference and tx vdda reference for use with external balun. can also be used as a control signal for external lna, pa, or t/r switch. 4 nc tie to ground. 5 pao_p rf output /dc input rf power amplifier output positive. open drain. connect to vdda through a bias network when used with an external balun. not used when internal t/r switch is used. 6 pao_m rf output/dc input rf power amplifier output negative. open drain. connect to vdda through a bias network when used with an external balun. not used when internal t/r switch is used. 7 sm input test mode pin. must be grounded for normal operation. 8 gpio4 1 digital input/ output general purpose input/output 4. see footnote 1 9 gpio3 digital input/ output general purpose input/output 3. 10 gpio2 digital input/ output general purpose input/output 2. when gpio_alt_en, register 9, bit 7 = 1, gpio2 functions as a ?crc valid? indicator. 11 gpio1 digital input/ output general purpose input/output 1. when gpio_alt_en, register 9, bit 7 = 1, gpio1 functions as an ?out of idle? indicator. 12 rst digital input active low reset. while held low, the ic is in off mode and all internal information is lost from ram and spi registers. when high, ic goes to idle mode, with spi in default state.
mc13202 technical data, rev. 1.2 16 freescale semiconductor 13 rxtxen 2 digital input active high. low to high transition initiates rx or tx sequence depending on spi setting. should be taken high after spi programming to start rx or tx sequence and should be held high through the sequence. after sequence is complete, return rxtxen to low. when held low, forces idle mode. see footnote 2 14 attn 2 digital input active low attention. transitions ic from either hibernate or doze modes to idle. see footnote 2 15 clko digital output clock output to host mcu. programmable frequencies of: 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, 62.5 khz, 32.786+ khz (default), and 16.393+ khz. 16 spiclk 2 digital clock input external clock input for the spi interface. see footnote 2 17 mosi 2 digital input master out/slave in. dedicated spi data input. see footnote 2 18 miso 3 digital output master in/slave out. dedicated spi data output. see footnote 3 19 ce 2 digital input active low chip enable. enables spi transfers. see footnote 2 20 irq digital output active low interrupt request. open drain device. programmable 40 k ? internal pull-up. interrupt can be serviced every 6 s with <20 pf load. optional external pull-up must be >4 k ? . 21 vddd power output digital regulated supply bypass. decouple to ground. 22 vddint power input digital interface supply & digital regulator input. connect to battery. 2.0 to 3.4 v. decouple to ground. 23 gpio5 1 digital input/output general purpose input/output 5. see footnote 1 24 gpio6 digital input/output general purpose input/output 6. 25 gpio7 digital input/output general purpose input/output 7. 26 xtal1 input crystal reference oscillator input. connect to 16 mhz crystal and load capacitor. table 8. pin function description (continued) pin # pin name type description functionality
mc13202 technical data, rev. 1.2 freescale semiconductor 17 27 xtal2 input/output crystal reference oscillator output note: do not load this pin by using it as a 16 mhz source. measure 16 mhz output at pin 15, clko, programmed for 16 mhz. see the mc13202 reference manual for details. connect to 16 mhz crystal and load capacitor. 28 vddlo2 power input lo2 vdd supply. connect to vdda externally. 29 vddlo1 power input lo1 vdd supply. connect to vdda externally. 30 vddvco power output vco regulated supply bypass. decouple to ground. 31 vbatt power input analog voltage regulators input. connect to battery. decouple to ground. 32 vdda power output analog regulated supply output. connect to directly vddlo1 and vddlo2 externally and to pao through a bias network. note : do not use this pin to supply circuitry external to the chip. decouple to ground. ep ground external paddle / flag ground. connect to ground. 1 the transceiver gpio pins default to inputs at reset. ther e are no programmable pullups on these pins. unused gpio pins should be tied to ground if left as inputs, or if left unc onnected, they should be programm ed as outputs set to the low state. 2 during low power modes, input must remain driven by mcu. 3 by default miso is tri-stated when ce is negated. for low power operation, miso_h iz_en (bit 11, register 07) should be set to zero so that miso is driven low when ce is negated. table 8. pin function description (continued) pin # pin name type description functionality
mc13202 technical data, rev. 1.2 18 freescale semiconductor figure 10. pin connections (top view) 1 2 3 gpio3 gpio2 gpio1 rst rxtxen attn clko spiclk 4 5 6 7 8 ct_bias rfin_p nc pao_p pao_m sm gpio4 rfin_m vddint gpio5 vddd irq ce miso mosi gpio6 12 13 14 15 16 11 10 9 24 23 22 21 20 19 18 17 vdda vbatt vddvco vddlo1 vddlo2 xtal2 xtal1 gpio7 ep 29 28 27 26 25 30 31 32 mc13202
mc13202 technical data, rev. 1.2 freescale semiconductor 19 8 crystal oscillator reference frequency this section provides application sp ecific information regarding crysta l oscillator reference design and recommended crystal usage. 8.1 crystal oscillator design considerations the 802.15.4 standard requires that several frequency tolerances be kept within 40 ppm accuracy. this means that a total offset up to 80 ppm between tran smitter and receiver will s till result in acceptable performance. the mc13202 transceiver provides onboard crys tal trim capacitors to a ssist in meeting this performance. the primary determining factor in me eting this specification is the to lerance of the crystal oscillator reference frequency. a number of fact ors can contribute to this toleran ce and a crystal specification will quantify each of them: 1. the initial (or make) tolerance of the crystal resonant frequency itself. 2. the variation of the crystal res onant frequency with temperature. 3. the variation of the crystal resonant frequency with time , also commonly known as aging. 4. the variation of the crystal re sonant frequency with load cap acitance, also commonly known as pulling. this is affected by: a) the external load capacitor values - init ial tolerance and variation with temperature. b) the internal trim capacitor values - initial tolerance and variation with temperature. c) stray capacitance on the crystal pin nodes - incl uding stray on-chip capaci tance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. whether or not a frequency trim st ep will be performed in production freescale requires the use of a 16 mhz crystal with a <9 pf load capacitance. the mc13202 does not contain a reference divider, so 16 mhz is the only frequency that can be used. a crysta l requiring higher load capacitance is prohibited because a higher lo ad on the amplifier circuit may compromise its performance. the crystal manuf acturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. the osci llator amplifier configuration used in the mc13202 requires two balanced load capacitors from each terminal of the crysta l to ground. as such, the capacitors are seen to be in series by the crystal, so each must be <18 pf for proper loading. in the figure 11 crystal reference schematic, the external lo ad capacitors are shown as 6.8 pf each, used in conjunction with a crystal that requires an 8 pf load capacitance. the default internal trim capacitor value (2.4 pf) and stray capacitance total value (6.8 pf) sum up to 9.2 pf giving a total of 16 pf. the value for the stray capacitance was determin ed empirically assuming the default internal trim capacitor value and for a specific board layout. a different board layout may re quire a different external load capacitor value. the on-chip trim capability may be us ed to determine the closest standard value by adjusting the trim value via the spi and observing the frequency at clko. each internal trim load capacitor has a trim range of approximately 5 pf in 20 ff steps.
mc13202 technical data, rev. 1.2 20 freescale semiconductor figure 11. mc13202 modem crystal circuit initial tolerance for the internal trim capacitance is approximately 15%. since the mc13202 contains an on-chip reference frequency trim cap ability, it is possible to trim out virtually all of the initial tole rance factors and put th e frequency within 0.12 ppm on a board-by-board basis. individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trim ming procedure. this st ep can be avoided by using/specifying a crystal with a tighter stability tolerance, but the crysta l will be slightly higher in cost. a tolerance analysis budget may be created using all the previously stated factors. it is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using rss (root-sum-squa re) analysis. the aging factor is usually specified in pp m/year and the product designer can dete rmine how many years are to be assumed for the product lifetime. taki ng all of the factors into account, the product designer can determine the needed specifications for the crystal and ex ternal load capacitors to meet the 802.15.4 standard. 8.2 crystal requirements the suggested crystal specificat ion for the mc13202 is shown in table 9 . a number of the stated parameters are related to desired package, desired te mperature range and use of crystal capacitive load trimming. for more design details and su ggested crystals, see application note an3251, reference oscillator crystal requirements for mc1319x, mc1320x, and mc1321x . table 9. mc13202 crystal specifications 1 1 user must be sure manufacturer specif ications apply to the desired package. parameter value unit condition frequency 16.000000 mhz frequency tolerance (cut tolerance) 2 2 a wider frequency tolerance may acceptable if app lication uses trimming at production final test. 10 ppm at 25 c frequency stability (temperature drift) 3 15 ppm over desired temperature range aging 4 2 ppm max equivalent series resistance 5 43 ? max load capacitance 6 5 - 9 pf shunt capacitance <2 pf max mode of oscillation fundamental y1 16mhz c10 6.8pf c11 6.8pf y1 = daishinku kds - dsx321g zd00882 xta l 1 26 xta l 2 27 u6 mc1320x
mc13202 technical data, rev. 1.2 freescale semiconductor 21 8.3 low power considerations ? program and use the modem io pi ns properly for low power operation ? all unused modem gpiox signals must be used one of 2 ways: ? if the off mode is to be us ed as a long term low power m ode, unused gpio should be tied to ground. the default gpio mode is an input and there will be no conflict. ? if only hibernate and/ or doze modes are used as long te rm low power modes, the gpio should programmed as outputs in the low state. ? when modem gpio are used as outputs: ? pullup resistors should be provi ded (can be provided by the mcu io pin if tied to the mcu) if the modem off condition is to be used as a long term low power mode. ? during hibernate and/or doze modes, the gp io will retain its programmed output state. ? if the modem gpio is used as an input, the gpio should be driven by its source during all low power modes or a pullup resi stor should be provided. ? digital outputs irq , miso, and clko: ? miso - is always an output. during hibern ate, doze, and active modes, the default condition is for the miso output to go to tristate when ce is de-asserted, and this can cause a problem with the mcu because one of its i nputs can float. program control_b register 07, bit 11, miso_hiz_en = 0 so that miso is driven low when ce is de-asserted. as a result, miso will not float when doze or hibernate mode is enabled. ?irq - is an open drain output (od) and shoul d always have a pullup resistor (typically provided by the mcu io). irq acts as the interrupt request output. note it is good practice to have the irq interrupt input to the mcu disabled during the hardware reset to the modem. after releasing the modem hardware reset, the interrupt request input to the mcu can then be enabled to await the irq that signifies the modem is re ady and in idle mode; this can prevent a possible extraneous false interrupt request. ? clko - is always an output. during hibernate clko retains it s output state, but does not toggle. during doze, clko may toggle de pending on whether it is being used. ? if the mcu is also going to be used in low power modes, be sure that all unused io are programmed properly for low power operation (t ypically best case is as outputs in the low state). the mc13202 is commonly used with the freescale mc9s 08gt/gb 8-bit devices. for these mcus: ? use only stop2 and stop3 modes (not stop1) wi th these devices where the gpio states are retained. the mcu must retain control of the mc13202 io during low power operation. ? as stated above all unused gp io should be programmed as out puts low for lowest power and no floating inputs. 3 a wider frequency stability may be acceptable if a pplication uses trimming at production final test. 4 a wider aging tolerance may be acceptable if applic ation uses trimming at production final test. 5 higher esr may be acceptable with lower load capacitance. 6 lower load capacitance can allow higher esr and is better for low temperature operation in doze mode.
mc13202 technical data, rev. 1.2 22 freescale semiconductor ? mc9s08gt devices have io signals that are not pinned-out on th e package. these signals must also be initialized (even though they ca nnot be used) to prevent floating inputs. 9 transceiver rf configurations and external connections the mc13202 radio has features that allow for a flexible as well as low cost rf interface: ? programmable output power ? 0 dbm nominal output power, programmable from -27 dbm to +4 dbm typical ? <-94 dbm (typical) receive se nsitivity ? at 1% per, 20- byte packet (well above 802.15.4 standard of -85 dbm) ? optional integrated transmit/recei ve (t/r) switch for low cost op eration ? with internal pas and lna, the internal t/r switch al lows a minimal part count radio interface using only a single balun to interface to a single-ended antenna ? maximum flexibility ? there are fu ll differential rf i/o pins for use with the internal t/r switch. optionally, these pins become the rf_in signals and a separate set of full differential pa outputs are also provided. separa te inputs and outputs allow for a vari ety of rf confi gurations including external lna and pa for increased range ? ct_bias output ? the ct_bias sign al provides a switched bias refe rence for use with the internal t/r switch, and alternatively ca n be programmed as an antenna switch signal for use with an external antenna switch ? onboard trim capability for 16 mhz crystal refe rence oscillator ? the 802.15.4 standard puts a +/- 40 ppm requirement on the car rier frequency. the onboard trim cap ability of the modem crystal oscillator eliminates need for external variab le capacitors and allows for automated production frequency calibration. also tighter tolera nce can produce greater receive sensitivity 9.1 rf interface pins figure 12 shows the rf interface pins and the associated analog blocks. notice that separate pa blocks are associated with rfin_x and pao _x signal pairs. the rf interface al lows both single port differential operation and dual port di fferential operation.
mc13202 technical data, rev. 1.2 freescale semiconductor 23 figure 12. rf interface pins 9.1.1 single port operation the integrated rf switch allows us ers to operate in a single port conf iguration. in single port mode, an internal rx switch and separate pa are used and pins rfin_p (p ao_p) and rfin_m (pao_m) become bidirectional and connect both for tx and rx. when receiving, the rx switch is enabled to the internal lna and the tx pa is disabled. when transmitting, th e rx switch is disabled (isolating the lna) and a tx pa is enabled. the optional ct_b ias pin provides a reference or bi as voltage which is at vdda for transmit and is at gr ound for receive. this signal can be used to provide the proper bias voltage to a balun that converts a single-ended antenna to the di fferential interface requi red by the transceiver. figure 13 shows a single port example with a balun. figure 13. single port rf operation with a balun the ct_bias is connected to the balun center-tap providing the prope r dc bias voltage to the balun depending on rx or tx. rx switch pa1 enable ct_bias control pa1 pa2 from tx psm rx enable lna rx signal rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m 2 1 3 5 6 pa2 enable ct_bias generator balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc13202/03 l1
mc13202 technical data, rev. 1.2 24 freescale semiconductor 9.1.2 dual port operation a second set of pins designated pao_p and pao_n al low operation in a dual port configuration. there are separate paths for transmit a nd receive with the optional ct_bias pin providing a signal that indicates if the radio is in tx or rx mode which then can be used to drive an external low noise amplifier, power amplifier, or antenna switch. in dual port operation, the rfin_p and rfin_n are inputs only, the internal rx switch to the lna is enabled to receive, and the associated tx pa st ays disabled. pins pao_p and pao_n become the differential output pi ns and the associated tx pa is enabled for transmit. figure 14 shows two dual port configurations . first is a single antenna confi guration with an external low noise amplifier (lna) for greater range. an external antenna switch is used to multiplex the antenna between receive and transmit. an lna is in the receive path to add gain for greater receive sensitivity. two external baluns are required to convert the sing le-ended antenna switch sign als to the differential signals required by the radio. separate rfin and pao signals are provided for connection with the baluns, and the ct_bias signal is pr ogrammed to provide the exte rnal switch control. the polarity of the external switch control is selectable. figure 14 also shows a dual antenna confi guration where there is a rx an tenna and a tx antenna. for the receive side, the rx antenna is ac -coupled to the differential rfin i nputs and these capacitors along with inductor l1 form a matching network. inductors l2 and l3 are ac-coupled to ground to fo rm a frequency trap. for the transmit side, the tx antenna is connected to the differential pao outputs, and inductors l4 and l5 provide dc-biasing to vdda but are ac-isolated. ct_b ias is not required or used.
mc13202 technical data, rev. 1.2 freescale semiconductor 25 figure 14. dual port rf configuration examples balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias (ant sw ctl) pao_p pao_m mc13202/03 lna ant sw balun vdd vdda bypass l1 using external antenna switch with lna rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc13202/03 vdda tx antenna bypass bypass l1 l2 l3 l4 l5 rx antenna using dual antenna
mc13202 technical data, rev. 1.2 26 freescale semiconductor 9.2 controlling rf modes of operation use of the rf interface pins and rf modes of ope ration are controlled through several bits of modem control_b register 07. figure 15 shows the model for register 07 wi th the rf interface control bits highlighted. figure 15. control_b register 07 model the rf interface control bits include: ? rf_switch_mode (bit 12) ? this bit selects dual port mode versus single port mode: ? the default condition (bit 12 = 0) is dual po rt mode where the rf inputs are rfin_m and rfin_p and the rf outputs are pao_m and pao_p, and operation is as described in section 9.1.2, ?dual port operation? . the use of ct_bias pin in du al port mode is controlled by bit 13 and bit 12. ? when bit = 1, the single port mode is se lected where rfin_m (pao_m) and rfin_p (pao_p) become bidirectional pins and operation is as described in section 9.1.1, ?single port operation? . the use of ct_bias pin in dual port mode in controlled by bit 13 and bit 12. ? ct_bias_en (bit 14) ? this bit is the enable fo r the ct_bias output. when bit 14 = 0 (default), the ct_bias is disabled and stay s in a hi-z or tri- stated condition. when bit 14 = 1, the ct_bias output is active and its st ate is controlled by the selected m ode (bit 12), ct_bias_inv, and operation of the radio. ? ct_bias_inv (bit 13) ? this bit only affects the st ate of ct_bias when dual port mode is selected and ct_bias is active. the ct_bia s changes state in dual port m ode based on the tx or rx state of the radio. the ct_bias_inv bit caus es the sense of the active stat e to change or invert based on bit 13?s setting. in this manner, the user can select the ct_bias as a control signal for external components and make the control si gnal active high or active low. register 07 0x07 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr_load ct_bias_en ct_bias_inv rf_switch_mode miso_hiz_en clko_doze_en tx_done_mask rx_done_mask use_strm_mode hib_en doze_en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0x0c00
mc13202 technical data, rev. 1.2 freescale semiconductor 27 table 10 summarizes the operation of th e rf interface control bits. 9.3 rf control output ct_bias ct_bias is a useful signal for interf ace with external rf components. it must be enabled via the ct_bias_en control bit, and then its state is determined first by th e selected rf mode and then by the active state of the radio, i.e., whether a tx or rx operation is active: ? single port operation ? in this mode, the ct_bias can be used to establish the proper dc bias voltage to a balun depending on the rx state versus tx state as described in section 9.1.1, ?single port operation? . note that in single port operation, the ct _bias_inv has no effect and ct_bias is at vdda for tx and is at ground for rx ? dual port operation ? in this m ode, the ct_bias can be used as a control signal to enable a lna or pa or to determine th e direction of an antenna switch as described in section 9.1.2, ?dual port operation? . in dual port operation, ct-bias_inv is used to control the sense of the output control, i.e., ct_bias can be active high or act ive low for tx and vice-versa for rx table 11 defines the ct_bias output state depending on c ontrol bits and operation mode of the modem. note that the output state is also defined in idle, hibernate, and do ze state as well as rx and tx operation. table 10. rf interface control bits bit designation default operation 14 ct_bias_en 0 1 = ct_bias enabled. output state is defined by table 11 . 0 = ct_bias disabled. output state is tri-stated. 13 ct_bias_inv 0 the output state of ct_bias under varying conditions is defined in table 11 . this bit only has effect for dual port operation. 1 = ct_bias inverted. 0 = ct_bias not inverted 12 rf_switch_mode 0 1= single port m ode selected where rf switch is active and rfin_m and rfin_p and bidirectional signals. 0 = dual port mode selected where rfin_m and rfin_p are inputs only and pao_p and pao_n are separate outputs. (this is default operation). table 11. ct_bias output vs. register settings mode ct_bias_en rf_switch_mode ct_bias_inv ct_bias rx 1 1 0 0 rx 1 1 1 0 rx 1 0 0 0 rx 0 x x hi-z rx 1 1 0 1 tx 1 1 0 1 tx 1 1 1 1 tx 1 0 0 1
mc13202 technical data, rev. 1.2 28 freescale semiconductor 9.4 rf single port appli cation with an f antenna figure 16 shows a typical single port rf a pplication in which part count is minimized and a printed copper f antenna is used for low cost. on ly the rfin port of the mc13202 is required because the differential port is bi-directional and uses the on-chip t/r switch. matching to near 50 ohms is accomplished with l1, l2, l3, and the traces on the pcb. a balun transforms the differential signal to single-ended to interface with the f antenna. the proper dc bias to the rfin_x (p ao_x) pins is provided through the balun. the ct_bias pin provides the proper bias voltage point to th e balun depending on operation, that is , ct_bias is at vdda voltage for transmit and is at ground for receive. ct_bias is switched between these two voltages based on the operation. capacitor c2 provides some high frequency bypass to the dc bias point. the l3/c1 network provides a simple bandpass filter to limit out-of-band harm onics from the transmitter. figure 16. rf single port application with an f-antenna tx 1 0 1 0 tx 0 x x hi-z idle 1 x x 0 idle 0 x x hi-z doze 1 x x 0 doze 0 x x hi-z hibernate 1 x x 0 (low-z) hibernate 0 x x hi-z offxxxunknown table 11. ct_bias output vs. register settings (continued) mode ct_bias_en rf_switch_mode ct_bias_inv ct_bias l2 6.8nh 5 1 6 2 3 4 z1 ldb212g4005c-001 l3 3. 9 n h c1 1.0pf r1 0r r2 0r not mount ed 1 2 5 3 4 j1 s ma_ e d ge _ r ec e p t a c c2 10pf an t1 f_antenna pao_m 6 pao_p 5 rfin_p 2 rfin_m 1 ct_bias 3 u5 mc 1 32 0 x l1 1.8nh l4 1.8nh
mc13202 technical data, rev. 1.2 freescale semiconductor 29 10 packaging information figure 17. outline dimensions for qfn-32, 5x5 mm (case 1311-03, issue e) n exposed die attach pad 2.95 25 8 1 32 3.25 32x 0.18 0.30 24 17 16 9 0.5 m 0.1 c m 0.05 c a b 32x 0.5 0.3 c 0.1 a b c 0.1 a b view m-m 0.25 28x detail m pin 1 index 2.95 3.25 pin 1 index area 5 b c 0.1 2x 2x c 0.1 a 5 g m m 1.0 1.00 0.05 c 0.1 c 0.05 c seating plane 5 detail g view rotated 90 clockwise (0.5) (0.25) 0.8 0.75 0.00 (1.73) (0.25) 0.065 32x 0.015 (45 ) 5 4 preferred corner configuration detail n 0.60 0.24 0.60 0.24 4 detail n corner configuration option detail t detail m backside pin 1 index option detail t backside pin 1 index option (90 ) 5 2x 2x 0.39 0.31 0.1 0.0 detail m backside pin 1 index option 1.6 0.475 0.425 1.5 backside pin 1 index 0.25 0.15 r detail s detail m preferred backside pin 1 index 0.217 0.137 (0.25) 0.217 0.137 (0.1) detail s preferred backside pin 1 index notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. the complete jedec designator for this package is: hf-pqfp-n. 4. corner chamfer may not be present. dimensions of optional features are for reference only. 5. coplanarity applies to leads, corner leads, and die attach pad. 6. for anvil singulated qfn packages, maximum draft angle is 12.
document number: mc13202 rev. 1.2 05/2007 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor d oes not convey any lice nse under its patent rights nor the rights of others. freescale semiconduc tor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other ap plications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal inju ry or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semico nductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005, 2006, 2007. all rights reserved.

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